Aswathi M P is a Senior ASIC Design Engineer at Synopsys Inc since November 2022, bringing expertise in RTL design with a focus on Wireless FPGA from previous roles at Tata Elxsi. Aswathi held positions as both an RTL Design Engineer and a Senior RTL Design Engineer during tenure at Tata Elxsi from November 2019 to November 2021. Academic qualifications include a Bachelor of Technology in Electronics and Communications Engineering from Mar Athanasius College of Engineering, completed in 2019.
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