Avinash A. is a Principal Engineer specializing in Layout Design at Synopsys Inc, with over 10 years of experience in analog and IO layout design. They have successfully designed a range of complex components, including 4nm ESD clamps and memory test chips, while also improving layout design efficiency through scripting. Previously, Avinash worked at ST Microelectronics and KPIT Cummins Infosystems Limited, demonstrating a solid foundation in the field. They earned an M.Tech in Micro-Electronics from Panjab University.
Location
Noida, India
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