Avinash A. is a seasoned Layout Design Sr. Staff Engineer at Synopsys Inc, specializing in analog and I/O layout design with over 10 years of experience. They have contributed to the successful tape-out of memory test chips and optimized layout designs for various technologies, including 4nm and 14nm processes. Avinash has a strong background in EDA tools and physical verification, having worked with leading fabs such as TSMC and Intel. They hold an M.Tech in Micro-Electronics from Panjab University.
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