Ayush G

Ayush G is a Digital Design Staff Engineer at Synopsys Inc, with experience in developing test benches using Verilog, System Verilog, and UVM since November 2024. Prior roles include Design Lead at Cadence from October 2021 to November 2024, focusing on IP design and DDR DRAM controller testbench development, and Design Engineer at Xilinx from March 2019 to September 2021, specializing in SOC verification and application of AI in accelerator cards. Previously, Ayush worked as an Associate Engineer at Synopsys Inc, contributing to UVM test bench development for Ethernet IP and RTL design, and held research assistant positions at Bharat Electronics and the Defence Research Organization of India, gaining insights into radar communication and microwave technology. Educational qualifications include a Master of Technology (MTech) in VLSI from C-DAC, Noida, and a degree in Electronics and Communication Engineering from Maharaja Surajmal Institute of Technology.