Bhawarth Gupta is an R&D Engineer at Synopsys, specializing in SRAM Embedded Memory Design with three years of hands-on experience in developing high-performance, low-power memory IP for advanced semiconductor nodes. They have contributed to successful tapeouts at leading-edge technology nodes, including 3nm and 5nm, directly supporting System on Chip (SoC) integration in various applications such as consumer electronics, automotive, and IoT. Bhawarth's dedication to pushing memory performance boundaries is matched by their passion for collaborative innovation and engineering excellence. Prior to their current role, they acquired experience as a Graduate Technical Intern and participated in workshops and webinars related to VLSI design. Bhawarth holds a Bachelor of Technology in Electronics and Telecommunications from Bharati Vidyapeeth, completed in 2022.
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