biral patel

Biral Patel is currently an ASIC Layout Designer at Synopsys Inc Technologies Pvt Ltd, previously known as Hewlett Packard Enterprise, and has several years of experience in the Design and Layout domain. Earlier in their career, they completed a one-year internship at STMicroelectronics, where they engaged in physical verification of layouts and dealt with DRC, LVS, DFM, and LFD issues while working on various technologies. Biral holds an M.Tech in VLSI Design from Nirma Institute and a B.E. in Electronics and Communication from Government Engineering College Modasa. They have participated in several IP verification and validation projects and are seeking opportunities to further enhance their skills.