Blade Lin is a Senior Manager of Physical Design at Synopsys Inc, where they currently oversee ASIC implementation tasks and have extensive experience with EDA tools from various vendors including Cadence and Synopsys. With a strong background in ASIC design methodologies from RTL to GDSII, they have previously held roles ranging from Senior ASIC Application Engineer at Goya Technology to Senior Physical Design Engineer at Synopsys. Blade's expertise encompasses logic synthesis, formal verification, and physical design for advanced node technologies, having supported multiple tier-1 customers throughout their career.
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