Brad Pierce

Brad Pierce has extensive experience in the field of electronic design automation, currently serving as an R&D Manager for the HDL Compiler at Synopsys Inc since 2002. In this role, Brad oversees a team of five senior developers and is responsible for the RTL-reading front-end that converts VHDL or SystemVerilog to a technology netlist for synthesis. Brad's expertise in SystemVerilog is further demonstrated through leadership as Co-Chair of the SV-BC technical committee for IEEE Std 1800, contributing to multiple revisions of the standard from 2005 to 2017. Prior experience includes serving as the SystemVerilog 3.1a BNF Annex Editor at Accellera Systems Initiative and as an R&D Engineer at Cadence Design Systems, focusing on place-and-route solutions. Brad holds a Ph.D. in Computer Science from UCLA.