Bramh Dev Singh

Bramh Dev Singh is a Staff Analog Design Engineer at Synopsys Inc., where they focus on analog design and verification. They previously held the position of Mixed Signal Design Engineer at HCLTech and served as an intern at Sankalp Semiconductor, working on modeling and analysis of Sigma-Delta ADC and modulator's non-idealities. Bramh holds a Master of Technology in VLSI Design from the Indian Institute of Engineering Science and Technology and has published research on Delta-Sigma ADC modeling at an IEEE conference in Japan. They also volunteered at the India International Science Festival and Vidyarthi Vigyan Manthan.