Chandan Gupta is a VLSI Layout Designer with over 2 years of experience, specializing in the design of GPIO, EMMC-PHY, I3C, I2C, and LVDS IPs. Chandan has worked on advanced nodes including N3E, N3P, N3A, N4P, N5, and N7A. Previously, Chandan served as an Embedded Engineer at Trydan Motors Private Limited from 2019 to 2020 and currently holds the position of A&MS Layout Design Senior Engineer at Synopsys Inc. Chandan earned an M.Sc. in Electronics from Delhi University and a B.Sc. in Electronic Science from Rajdhani College University of Delhi.
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