Chaoqun Wei is a highly motivated and innovative Senior Staff ASIC Digital Design Engineer at Synopsys Inc, where they have been since 2014, serving as the design owner of the DesignWare ARC VPX DSP Processor IP. Previously, Chaoqun was a Graduate Student at UCLA from 2012 to 2014, focusing on ASIC design and verification, and completed a technical internship at Synopsys Inc in digital IP design. Chaoqun holds both a Bachelor's degree and a Master's degree in Electrical and Electronics Engineering from Zhejiang University and UCLA, respectively.
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