Chienmin Lee is a seasoned professional in the field of R&D, currently serving as a Senior Manager at Synopsys Inc since December 2012. In this role, Chienmin Lee oversees the Verdi SystemVerilog compiler front-end and has previously held positions such as Manager II and R&D Engineer Sr. I, focusing on maintenance and enhancement of the compiler and the management of the Verdi knowledge database. Prior experience includes working as an R&D Engineer at SpringSoft from December 2009 to November 2012, where responsibilities involved maintaining the Verilog/SystemVerilog parser and overseeing the knowledge database for Verdi. Chienmin Lee holds a Master of Science and a Bachelor of Science in Computer Science from National Tsing Hua University, completed in 2009 and 2007 respectively.
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