Darshit Pandya

Darshit Pandya is a seasoned engineer with a comprehensive background in silicon design and verification. With experience as a Sr. Silicon Design Engineer at AMD, Darshit was responsible for RAS feature management across SOC, focusing on developing and designing test cases for error injection in various SOC IPs. Previous roles include Graduate Engineer and Verification Engineer at Arm, where Darshit worked on design verification for CPU architectures and developed directed test-cases for V9 compliant CPUs. Experience also includes positions at Matrix Comsec as a Trainee Software Developer, Synopsys Inc as a Sr. Staff Engineer, MediaTek as a Staff Engineer specializing in RISC-V UVC development, and Samsung Semiconductor focusing on CPU-AP interface verification. Darshit holds a Bachelor’s degree in Electronics and Communication Engineering from R.K. College of Engineering & Technology and a Master’s degree in Communication Engineering from Nirma University, Ahmedabad.