Dasaradh Patibandla

Dasaradh Patibandla is a Staff Analog Circuit Design Engineer with over 6 years of experience focused on high-speed SERDES receivers, transmitters, and clocking systems. They have worked with industry leaders such as GF, TSMC, and Samsung, specializing in CML-based 112Gbps designs and PCIe interface equalizers. Previously, Dasaradh held positions at VEDA IIT and INVECAS, where they developed critical skills in analog design. Currently, they are pursuing a Master’s degree in Electrical and Computer Engineering at the University of Florida.