Deepak Agrawal

Deepak Agrawal is a Senior ASIC Digital Design Engineer at Synopsys, where they are currently engaged in advanced digital design and verification. A graduate in Electronics and Communication Engineering from ABES Engineering College, Deepak has developed a strong foundation in Verilog, System Verilog, and various aspects of RTL creation and debugging. Their experience includes working with cross-functional teams on synthesis and integration, as well as preparing automated verification flows using TCL. Previous roles included positions as Design Engineer Trainee and Design Engineer II at Vervesemi, where they honed their expertise in digital design.