DEEPAK BHADU

Deepak Bhadu is a seasoned professional in physical design engineering with experience spanning from 2019 to the present. Beginning as a Physical Design Trainee at VLSIGuru Training Institute, Deepak honed skills in Full PnR flow using Synopsys ICC and executed tasks including Floor Planning and Timing analysis. Deepak advanced to a Design Engineering Intern position where contributions were made to Cadence’s first 12LP/LP+ memory IP solution. At Cadence Design Systems, Deepak served as a Senior Design Engineer, specializing in high-speed DDR PHY hardening for multiple clients, with responsibilities encompassing IO Ring planning, RDL, Floorplan, CTS, PnR, and Signoff. Currently, as a Staff Physical Design Engineer at Synopsys Inc., Deepak focuses on block level implementation of Serdes IPs, managing Floorplan, PnR, CTS, PV, IREM, and STA. Educational background includes a degree from the National Institute of Technology Kurukshetra where Deepak acted as a Research Scholar.