Deepak Nagaria is an R&D Senior Staff member at Synopsys, where they have contributed to projects involving advanced memory technologies such as DDR5 and LPDDR5. They previously held various R&D engineering roles at Synopsys from 2017 to 2018, working on UCIe adapters and JEDEC standards. Prior to this, they served as a Design and Verification Engineer at Arrow Devices from 2013 to 2015, focusing on MIPI and USB PHY designs. Deepak earned a PG Diploma in VLSI Design from CDAC in 2013.
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