Devanshi Saxena

Devanshi Saxena is an R&D Engineer, SR1 at Synopsys Inc with over five years of experience in the VLSI industry, specializing in System Verilog, Verilog, UPF, and Power Estimation with ZeBu-Emulation. They previously held roles including Application Engineer Sr I and intern at the same company. Devanshi earned a Bachelor's Degree in Electronics and Communications Engineering from Krishna Engineering College and a Master's Degree in VLSI Design from Manipal University, demonstrating a strong academic foundation in their field.