Dhruv Garg

Dhruv Garg is a Verification IP Developer at Synopsys, specializing in high-speed storage access protocols like NVMe and CXL. They have rich experience in creating and executing verification plans, as well as developing various features of these protocols using SystemVerilog and UVM. Dhruv completed a Master of Technology in VLSI Design from Dr. B. R. Ambedkar National Institute of Technology, Jalandhar, and holds a Bachelor of Technology in Electronics and Communication Engineering from Jaypee Institute of Information Technology. Prior to joining Synopsys, Dhruv served as a Teaching Assistant and had roles as a Lead Member of Technical Staff and Verification Intern at Siemens EDA.