Dinesh Sehra

Principal Engineer

Dinesh Sehra is an MBIST expert and a front-end design and verification engineer with extensive experience in memory IP verification. With a B.Tech. degree from the National Institute of Technology Calicut, Dinesh has worked at leading companies including Broadcom Limited and Synopsys Inc, focusing on ASIC design and validation. Currently serving as an Expert 1 at Capgemini, Dinesh has contributed to numerous high-profile projects, including OVM verification of BISTed memory hard-mac at 7nm and front-end design of dual port memory at 16nm.

Location

Noida, India

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