Dipak Patil

Dipak Patil is an R&D Sr. Staff at Synopsys Inc, bringing around five years of industry experience in SoC verification and the development of verification IP using System Verilog. Dipak has a strong background in coverage-driven constrained random verification with exposure to various on-chip bus architectures, including AMBA 5, ACE, and AXI. They have previously held positions at Emulex as an ASIC Verification Intern and at Synopsys in multiple roles, focusing on verification methodologies and testbench development. Dipak earned an MTech in VLSI from the National Institute of Technology Karnataka and a Bachelor of Engineering in Electronics and Telecommunication from the University of Pune.