Divagar T is an experienced ASIC digital design professional currently serving as a Staff Engineer at Synopsys Inc since 2025. Prior to this role, they worked as a Design Engineer at Tessolve from 2023 to 2025 and as a Verification Engineer at SmartDV Technologies India Private Limited from 2019 to 2023. Their diverse expertise in engineering highlights their commitment to advancing in the field of digital design.
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