Divyesh U.

Divyesh U. is a Senior Staff R&D Engineer at Synopsys, specializing in architecture FV, verification, SAT/SMT solvers, ATP, and compilers. They previously held positions as a Scientist and Senior Research Software Engineer at Tata Consultancy Services and as a Research Scholar at the Indian Institute of Technology Bombay, where they earned a Ph.D. in Software Verification. Divyesh has a strong focus on software verification, AI, and compiler techniques, and their work has led to multiple publications and accolades in the field. In leisure, Divyesh enjoys sports, cooking, music, and exploring nature.