Dr. Patrick Juliano is currently a Senior Manager and Design Automation Lead for Interface IP at Synopsys Inc, where they drive innovative methodologies and robust design processes across the DDR PHY team. Previously, they held various leadership roles at Intel Corporation, managing teams that delivered high-quality solutions for system-on-a-chip products and receiving multiple accolades for outstanding performance. Dr. Juliano also contributed to the development of critical ESD protection circuits during their time at Hewlett-Packard and has authored patents and technical papers, demonstrating their expertise in electrical engineering and circuit design. They are pursuing a PhD in Electrical Engineering at the University of Illinois Urbana-Champaign.
This person is not in any teams
This person is not in any offices