Duc Thanh

Duc Thanh is a seasoned professional in SoC and RTL design, currently working as a SoC Design Engineer at Intel Corporation since November 2022 and serving as a Sr. Staff Engineer in ASIC Digital Design at Synopsys Inc. starting in November 2023. Previous experience includes a role as a Senior RTL Design Engineer at Arrive Technologies, where involvement in projects such as AT4848 and Thalassa focused on clock synchronization systems for SONET/SDH cards. Duc Thanh has also contributed to the design of 4-channel LTE transmitters and Altera IP cores at Altera, and has been with Viettel since March 2013, designing and verifying wireless IP cores for 4G and 5G networks. Educational background includes a degree from Ho Chi Minh University of Technology, completed in 2006.