Fatemeh Negin Javaheri

Fatemeh Negin Javaheri, PhD, is a detail-oriented and self-motivated RTL Design Engineer with over 15 years of experience in FPGA digital circuit design and verification. They have led various projects, including the "ESL Design Methodology" project at the University of Tehran and developed the SyntHorus2 tool while at TIMA lab. Currently, Fatemeh works as a Principal Engineer in ASIC Digital Design at Synopsys Inc, following a position as an Engineering Manager at Intel Corporation. They hold a PhD in Electrical and Electronics Engineering from the Institut national polytechnique de Grenoble and have a strong commitment to continuous learning and adapting to industry trends.