Febin Francis C is a Staff Engineer at Synopsys Inc, where they focus on RTL and SoC-based design development. Previously, they served as a Senior Design Engineer at Mistral Solutions Pvt. Ltd and held the position of Module Lead at an aerospace and defense company. With a background in RTL design, VHDL coding, and FPGA development, Febin has experience in static timing analysis and customized IP implementation. They hold a Bachelor of Technology in Electrical, Electronics, and Communications Engineering from the College of Engineering, Chengannoor, and a postgraduate diploma in Embedded System Design from Cranes Varsity. Passionate about continuous learning, Febin also enjoys music and traveling.
Location
Kerala, India
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