Febin Sebastian is a Senior ASIC Design Engineer at Synopsys Inc, with a strong background in ASIC based RTL design, simulation, and debugging. Previously, Febin worked at Wipro as a Senior ASIC Design Engineer and at Cerium Systems as a Senior RTL Design Engineer. Febin began their career as an RTL Design Engineer at Avench Systems Pvt Ltd, contributing to innovative projects such as the Pipeline Investigation Gauge. Febin holds a Master of Technology in VLSI from Sathyabama University and a Bachelor's degree in Electrical, Electronics, and Communications Engineering from Vimal Jyothi Engineering College.
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