Fenglin Guan

Fenglin Guan is a Verification Manager at 新思科技 with over 8 years of experience in functional verification of RISC processors and SoCs. They possess strong knowledge in RISC CPU architectures and have demonstrated expertise in verifying various CPU modules and industry-standard bus protocols. Fenglin has experience leading verification teams and developing reusable verification environments while utilizing advanced methodologies such as UVM and formal verification techniques. They earned a Master's degree in Electrical and Electronics Engineering from the University of Electronic Science and Technology.