Fred Meyer

Fred Meyer is a results-oriented Principal DV Engineer at Synopsys Inc, with a successful track record as both a global team leader and technical contributor in ASIC verification. They developed and rolled out emulation transactors for complex storage protocols, significantly increasing revenue for their employer. Previously, Fred held positions at SEAKR Engineering and Andes Technology, focusing on design verification and embedded CPU cores. They co-authored industry methodology papers and actively contributed to global conferences. Fred is currently pursuing degrees in Circuit Design and Computer Engineering at San Jose State University and Santa Clara University, respectively.