Garima Tomar is currently pursuing a Bachelor of Technology in Electronics and Communication at Meerut Institute of Engineering and Technology. Garima has served as a Teaching Assistant at the National Institute of Technology, Kurukshetra from 2022 to 2023, and has gained industry experience as a Standard Cells Layout Design Senior Engineer at Synopsys Inc in 2024. Additionally, Garima has held an internship in Product Validation at Cadence Design Systems from 2023 to 2024 and previously interned in Standard Cells Layout Design. Garima is focused on VLSI Design and continues to advance their expertise in this field.
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