Garvit Goyal is currently a Staff A&MS Layout Design Engineer at Synopsys Inc, where they work on the 3nm technology node, focusing on the development of IOs and Cap Cells. With a strong background in layout design, Garvit has previously contributed to projects involving 4nm and 22nm technology nodes, and has experience with various design checks such as DRC and LVS. Garvit began their career with an internship at the Airports Authority of India and holds a Bachelor of Technology in Electronics and Communications Engineering from Inderprastha Engineering College Ghaziabad.
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