Gaurav Manocha

Gaurav Manocha is a Product Engineer with 10 years of experience in design and verification, currently working as a Staff R&D Engineer at Synopsys Inc. They specialize in PCIe, NVMe, and CXL protocols, having developed key features such as PCIe Transaction Layer and supported the deployment of PCIe Zebu Transactor at customer sites. Previously, Gaurav held various technical roles at Mentor Graphics and Siemens EDA, where they led verification development and contributed to multiple protocols. Gaurav earned a Bachelor of Technology in Electrical, Electronics, and Communications Engineering from ITM University and has undergone System Verilog training with Mentor Graphics.