Gelli Kavya

Gelli Kavya is a skilled Layout Design Senior Engineer at Synopsys, where they focus on Analog and Mixed Signal block level layout and custom memory layout. Prior experience includes working as a Layout Design Engineer and Associate Engineer at Micron Technology. Gelli has strong expertise in tools such as Calibre, Cadence Virtuoso, and Synopsys Custom Compiler, as well as in timing closure with PrimeTime. Gelli holds a Bachelor of Technology in Electronics and Communications Engineering from the National Institute of Technology Warangal and is currently pursuing a Master of Technology in Micro-electronics Engineering at the Birla Institute of Technology and Science, Pilani.