Greg Szczepkowski

Greg Szczepkowski is a Staff Analog Design Engineer at Synopsys, bringing extensive experience in various aspects of electronic engineering. They have held positions as a Principal Analog Design Engineer at Renesas Electronics and Dialog Semiconductor, and led the Integration/Analog team at Adesto Technologies. Greg completed a PhD in Microelectronics from the National University of Ireland, Maynooth, where they also worked as a Postdoctoral Researcher focusing on RF design. Their skills encompass a range of CAD tools, CMOS RF/Analog design, and advanced layout techniques.