Harsh Gupta

Harsh Gupta is a seasoned professional in the field of engineering and verification, currently serving as a Senior Manager in R&D at Synopsys Inc since January 2024. Prior to this role, Harsh held the position of Senior Design Manager at AMD from February 2022 to December 2023 and served as a Senior Engineering Manager at Xilinx, where responsibilities included managing a verification team for delivering next-generation FPGAs on 7nm technology. Harsh's extensive experience encompasses various roles across prominent companies including Rambus, Semtech, Cadence Design Systems, Agere Systems, DCM Technologies, Compaq, and Wipro Technologies, focusing on SoC verification and advanced methodologies to enhance quality and automation. Harsh holds an M.Tech in Electronics & Communication from IASE University and a BE in Electronics and Communication from Gulbarga University.