Harshadas C H

Harshadas C H is a Senior Staff Engineer with expertise in IP RTL design, particularly in DDR memory controllers, CHI, and AXI protocols. They have significant experience in RTL design and verification using Verilog and VHDL, as well as static timing analysis and board bring-up. Previously, Harshadas worked at CoreEL Technologies as both a Design Engineer and Senior Design Engineer, where they focused on Xilinx FPGA targeted RTL design and mentoring junior engineers. They have also held multiple roles at Synopsys Inc., advancing to Senior Staff Engineer, where they continue to apply their extensive skills in ASIC digital design. Harshadas earned a Bachelor’s degree in Electrical, Electronics, and Communications Engineering from N S S College of Engineering in 2013.