Harshdeep Verma

Harshdeep Verma is a dedicated semiconductor professional currently serving as a Staff Engineer at Synopsys since 2025. With over six years of experience in Design Verification, Harshdeep has expertise in functional verification using System Verilog and UVM, along with a strong grasp of various protocols including Ethernet and security standards like MACsec and IPsec. They have independently authored a technical paper presented at DVCon Taiwan 2023 and successfully filed a US patent for a low-latency timestamping method in communication systems. Harshdeep holds a Bachelor of Technology in Electronics Instrumentation and Control Engineering from YMCA University of Science & Technology, which they completed in 2017.