Hemakumar B

Hemakumar B is currently a Staff Engineer in Applications Engineering at Synopsys, where they lead Nex-Gen University Connects and specialize in the Design Verification domain within the VLSI industry. They possess strong knowledge in System Verilog, Verilog, and VHDL, as well as familiarity with Universal Verification Methodology (UVM). Previously, Hemakumar served as an Executive Engineer in R&D at Medha Servo Drives Pvt Ltd and held the position of Assistant Professor at Alamuri Ratnamala Institute of Engineering and Technology, where they taught Verilog, System Verilog, and Digital Design. Hemakumar obtained a Master’s Degree in Control Systems from the National Institute of Technology Kurukshetra and is currently pursuing a Bachelor of Technology at Sri Venkateswara University.