Honey Garg

Honey Garg is currently a Staff Engineer in the IO Design Team of the IP Group at Synopsys, where they focus on various aspects of circuit design. Previously, Honey completed internships at STMicroelectronics, where they conducted power-performance-area analyses and engaged in function validation for advanced technologies. Honey also held positions as a Design Engineer and Senior Engineer at Synopsys, contributing to multiple design projects, including Rx and Tx designs and fail-safe block construction. They hold a Bachelor's degree in Electronics and Communication Engineering from DAV Institute of Engineering and Technology and a Master's degree in VLSI Design from Punjab Engineering College.