Hui Ding is a seasoned professional in the field of R&D within the semiconductor design industry, currently serving as Senior Principal R&D at Synopsys Inc since July 2025. Prior to this role, Hui held various senior positions, including Senior Principal R&D Engineer at ANSYS, Inc. from March 2017 to July 2025, focusing on distributed/multithreading IR drop simulation and analysis as well as sparse/dense matrix solvers. Hui's experience also includes being an Architect at CLK Design Automation from April 2014 to March 2017, and contributing to timing simulation and analysis. Earlier roles at Cadence Design Systems included Senior Member of Consulting Staff, where work centered around timing library characterization and fast spice circuit simulation, along with R&D efforts at Altos Design Automation and Celestry Design Technologies, both acquired by Cadence.
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