Hyondeuk Kim

Hyondeuk Kim is currently a Senior Staff R&D Engineer at Synopsys Inc, where they develop and maintain formal verification algorithms in Synopsys VC Formal and Hector. They previously held the position of Staff R&D Engineer at Synopsys from 2018 to 2020. Prior to that, Hyondeuk worked as a Principal Software Engineer at Cadence Design Systems from 2011 to 2018, and completed research internships at NEC and Cadence Design Systems in 2006 and 2007, respectively. Hyondeuk earned a PhD in Electrical and Computer Engineering from the University of Colorado at Boulder, where they studied from 2003 to 2010.