Igor Melamed

Igor Melamed is an experienced ASIC Design Engineer at Synopsys Inc since 2014, with a robust career spanning over three decades in the electronics and telecommunications sectors. Previous roles include FPGA Team Leader at RuggedCom and Senior ASIC/FPGA Designer at Genband and Nortel Networks, showcasing a strong expertise in both ASIC and FPGA design. Igor's technical foundation was established at Cadence Design Systems as a Senior Field Application Engineer and further developed at RAD Data Communications and Telrad as a Senior ASIC Designer and ASIC Designer, respectively. Early career experience at Intel as a Component Designer laid the groundwork for a successful trajectory in engineering, supported by an Engineer's degree in Electrical and Electronics Engineering from Leningrad Politechnical Institute.