Jack Zhu

Jack Zhu is an accomplished R&D Engineering Scientist at Synopsys Inc, where since June 2017, Jack has served as the Lead Architect of DDR Controller IPs, including DDR5 controllers. Prior to this role, Jack held various significant positions at Marvell Semiconductor from September 2008 to June 2017, including Engineering Director / Principal Architect, overseeing IP projects across multiple business units, and as Principal Architect, leading the development of DDR Memory Controller IPs for over 20 SoCs. Jack's earlier experience includes roles at Vweb Corporation, where leadership in HD video codec SOC projects was demonstrated, as well as a Director of ASIC Design position focused on MPEG codec SOCs. Jack also worked at ESS Technology as an ASIC Design Manager, contributing to MPEG4 camcorder SOCs. Jack Zhu holds both a Master’s and Bachelor’s degree in Computer Science from Peking University.