Jagadish MJ is a Staff Engineer specializing in ASIC Design at Synopsys Inc, with a focus on VLSI front-end engineering and over six years of experience in RTL design and FPGA development across various platforms. Previously, Jagadish held roles as a Lead Engineer at Ensurity Technologies, FPGA Engineer at L&T Technology Services Limited, and Senior Project Engineer at Wipro. Currently pursuing a Doctor of Philosophy (PhD) at BITS Pilani, Hyderabad Campus, Jagadish also earned a Master of Technology in VLSI Design from Jawaharlal Nehru Technological University.
This person is not in the org chart
This person is not in any teams
This person is not in any offices