Jatin is a Senior Design Verification Engineer at Synopsys Inc, where they have been since 2023, following their role as a Research and Development Engineer from 2020 to 2022. Prior to joining Synopsys, they worked as a Product Validation Engineer and an Application Engineer at Cadence Design Systems from 2018 to 2019. Jatin earned a Bachelor of Technology in Electrical and Electronics Engineering from Sri Aurobindo College, completing their degree in 2017.
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