Jay Agrawal is a Senior Staff Engineer at Synopsys Inc, focusing on DFT, JTAG Boundary Scan, and LBIST. Prior to this role, Jay worked as a Senior DFT Engineer at Intel Corporation and was a Lead DFT Engineer at STMicroelectronics. Jay also gained experience at UTC Aerospace Systems as a System Engineer and at Cadence Design Systems as a DFT Engineer, where Jay contributed to the development of test cases. Jay earned a Bachelor of Technology in Electronics and Communications Engineering from IIIT Allahabad in 2014.
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