Jay Parekh

Jay Parekh is an accomplished ASIC Digital Design Staff Engineer at Synopsys Inc, with a career spanning from July 2021 to the present. Prior roles include ASIC Digital Design Engineer Sr I and ASIC Digital Design Engineer II at the same company, and an Associate ASIC Engineer at Softnautics LLP from May 2018 to July 2021, where responsibilities included extensive work on the Link Layer and PHY Layer of USB, as well as hands-on knowledge of MIPI DSI, CSI2, and D-PHY. Earlier experience includes an Engineering Project Trainee position at Physical Research Laboratory and serving as vice chair for the IEEE DDU Student Branch. Jay's educational background includes a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from Dharmsinh Desai University, along with prior studies in Science and Secondary Education.