Jay Roy

Jay Roy is an accomplished engineering executive with extensive experience in power optimization for system-on-chip (SOC) designs. Currently serving as Chief Architect and Group Director for Power Continuum at Synopsys Inc since May 2018, Jay Roy focuses on the integration of verification, implementation, and signoff processes for enhanced SOC power performance. Prior to this role, Jay Roy was a Group Director at Cadence Design Systems, where the development of Joules, a power calculator for RTL and Gates, was a significant achievement. With a career spanning over two decades in various leadership positions across renowned companies such as ANSYS Apache, Cadence Design Systems, and Sun Microsystems, Jay Roy has a proven track record in RTL Power Analysis and Optimization. Academic credentials include a PhD in Computer Engineering from the University of Cincinnati and a BTech in Electronics and Communications Engineering from the Indian Institute of Technology, Kharagpur.