Jayashankar M V

Jayashankar M V is a seasoned professional in layout design with significant experience in various leadership roles within the semiconductor industry. Currently serving as Principal Layout Design at Synopsys Inc since July 2023, Jayashankar contributes to the methodology team, focusing on enabling the latest technology and testing new methodologies. Prior to this, Jayashankar held the position of Manager Analog and Mixed Signal Layout at SiTime from February 2022 to June 2023, overseeing full chip layout activities and collaborating with design and layout teams. Previously at Synopsys Inc from March 2018 to February 2022, Jayashankar was Product Line Owner for 112G SERDES IP across multiple technology nodes, highlighting expertise in SerDes PHY sub-blocks. At SiCon Design Technologies Pvt. Ltd. from January 2013 to March 2018, Jayashankar managed a team of over 20 layout engineers as Technical Lead for RF-Modem applications. Earlier experience includes a role as Lead Engineer at Masamb Electronics Systems, focusing on standard cell library development.