Jenny (Junhong) Zhao is a Sr Staff Analog IC Designer at Synopsys, where they work on PLL design for multi-protocol Serdes IPs. They previously held the position of Senior Analog IC Designer at Intel Corporation, focusing on high-speed Serdes IPs for various technology nodes. Jenny's extensive background includes roles as an Analog/Mixed-Signal IC Designer at AMD, an RF Design Engineer at novero, and a Sr. RF Engineer at the NORTHWEST AIR TRAFFIC MANAGEMENT BUREAU of CAAC. They earned a Bachelor’s degree in Optical-electric & Scientific Instrument Engineering from Zhejiang University and a Master of Applied Science in Electrical and Computer Engineering from Concordia University.
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